Description Intersil 6100



die of intersil 6100.


the 6100 12-bit cpu closely emulates pdp-8 (see pdp-8 more complete discussion). has 3 primary registers: pc (program counter), 12-bit ac (accumulator), , mq. two-operand instructions read ac , mq , write ac. there no stack pointer; subroutines return callers jumping main code, typically storing return address in first word of subroutine itself. (not programs in rom.)


conditionals in 6100 allow next instruction skipped. branches constructed conditional , following jump. there 1 maskable interrupt. when interrupt tripped, cpu stores current pc in 0000, , jumps location stored in 0001. interrupt can disabled or enabled using iof , ion (or skon) instructions.


the 6100 has 12-bit data/address bus, limiting ram 4k words (6 kb). memory references 7-bit, offset either address 0, or pc page base address (obtained setting 7 least significant bits of pc zero). memory expanded using optional 6102 support chip, added 3 address lines , expanded memory 32k words (48 kb) in same way pdp-8/e expanded pdp-8. 6102 has 2 internal registers, ifr (instruction field register) , dfr (data field register), offset 4k page when cpu accesses memory.







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